1. Field of the Invention
The present invention relates to a method of transmitting data in a liquid crystal display, and more particularly, to a method of transmitting data from a timing controller to a source driving device in a liquid crystal display.
2. Description of the Related Art
In the display industry, the consistent trend is to move toward higher-resolution displays. However, increasing the resolution results in increasing the overall data rate both from the host (e.g., a graphic card) to the panel, and within the panel itself. By the late 1990s, resolutions for LCD (liquid crystal display) panels were moving from VGA (video graphics array) resolutions with a cumulative bandwidth requirement of slightly more than 300 Mbits/sec to XGA (extended graphics array) resolutions that required 850 Mbits/sec. Additionally, UXGA (ultra extended graphics array) resolution and its 2 Gbits/sec requirement loomed on the horizon. The increasing frequency was creating problems with the TTL (transistor-transistor logic) interface between the host and the LCD panel. Power consumption was ballooning, electromagnetic interference (EMI) was on the rise, and larger connectors and cables were required to meet the expanding number of data lines.
In 1999, National Semiconductor Corporation released the Open Low-Voltage Differential-Signaling Display Interface, or OpenLDI specification, which serialized 22 TTL signals down to four differential pairs. Because the new interface was low swing (±400 mV versus several volts for TTL) and differential, the total power and EMI were significantly reduced. Also, as the total number of wires was reduced from 22 down to eight, the connectors and cabling shrank, saving system cost and improving the mechanical connection between the host and the panel.
Once the issues of the host-panel interface were solved, similar issues occurred within the panel. National Semiconductor Corporation utilized the success of Low Voltage Differential Signaling (LVDS) and OpenLDI as a baseline for creating another open standard for the Reduced-Swing Differential-Signaling (RSDS) interface to solve intra-panel interface issues. The RSDS interface reduced the total number of wires from 72 (two 36-wide buses) to 20 (10 differential pairs), and the voltage swings were ±200 mV differential, reducing both the power and the EMI of the panel.
FIG. 1 shows a block diagram of an LCD module, which demonstrates an arrangement of an RSDS bus in the LCD module. The LCD module comprises an LCD panel 1 having plural thin film transistors disposed in a matrix form, a gate driving device 4 having plural gate driving units electrically connected to the gates of the thin film transistor through plural scan lines 41, a source driving device 3 having plural source driving units electrically connected to the sources of the thin film transistors through plural data lines 31, and a timing controller 2 receiving image data through a first bus 5, sending control signals to the gate driving device 4 through a second bus 6, and sending the image data to the source driving device 3 through an RSDS bus 7.
FIG. 2 shows the timing characteristics of a clock signal CLK, a start pulse STH and the image data signal RSR/G/B in accordance with the RSDS standard, where SPSU, SPHD, SPRS, RSSU and RSHD are the start pulse set up time, the start pulse hold time, the start pulse to data valid delay, the RSDS data setup time and the RSDS data hold time, respectively. The start pulse STH sent from the timing controller 2 is two clock cycles (or five clock edges) prior to the start of valid image data. Note that the RSDS standard uses both edges (rising and falling) of the clock to strobe data. In addition, FIG. 3 shows the diagram regarding the RSDS skew-setup/hole time control, due to the open nature of the RSDS standard, the RSSU and RSHD (i.e., setup/hold time) requirements for the start pulse STH and the image data signal RSR/G/B can vary from one channel to another or can vary under different scanning frequency. Therefore to assure the transmission of the image data from the timing controller 2 to the source driving device 3 in all channels, the timing controller 2 should be designed with the capability for setup/hold time adjustment. A conventional method of performing the setup/hold time adjustment is to adjust the skew control pins on a printed circuit board (PCB). The skew control pins can change a voltage swing of the image data for setup/hold time adjustment. Of course, any other kind of setup/hold time adjustment is also acceptable. Once the setup/hold time is set, the skew control pins have to be adjusted manually to meet the requirement of the source driving device 3 due to change of the scanning frequency.
Therefore, it is necessary to develop an automatic mechanism to select a proper setup/hold time so as to transmit the image data from the timing controller 2 to the source driving device 3 successfully.